(1) Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a semiconductor integrated circuit device in which memory cells are of an I.sup.2 L (which is an abbreviation for Integrated Injection Logic) type.
(2) Description of the Prior Art
In general, each of the memory cells of a bipolar memory device comprises a pair of load resistors connected to one word line, a pair of cross-coupled transistors which serve as a flip-flop, connected to the load resistors, respectively, to one hold line which forms a word line pair with said word line and to a pair of bit lines. In the bipolar memory cells, the resistance value of the load resistors is very large so as to reduce the power consumption thereof. Therefore, the area the load resistors occupy in a chip is very large, and in addition, isolation between the cross-coupled transistors is required. Consequently, the bipolar memory cells are large in size. This results in a low integration density, and, therefore, a high manufacturing cost of the bipolar memory device.
In recent years, an I.sup.2 L memory device has been developed. In an I.sup.2 L memory cell, a pair of load transistors which serve as injectors are used instead of the above-mentioned large load resistors and, in addition, no isolation between transistors within a row is required. As a result, a high integration density and a low manufacturing cost can be attained. It should be noted that, such an I.sup.2 L memory device can be manufactured by using conventional bipolar technology.
Usually, one I.sup.2 L memory cell comprises a pair of first and second transistors of a first conduction type, such as a pnp type, which serve as injectors, a pair of cross-coupled third and fourth transistors of a second conduction type, such as an npn type, which serve as a flip-flop and a pair of fifth and sixth transistors of the second conduction type for detecting or reversing the state of the flip-flop in a read-out or write mode, respectively. The third and fourth transistors are always in the reverse conducting mode, in other words, the emitters and collectors of these transistors are used as collectors and emitters, respectively. In addition, when the memory cell is non-selected, the fifth and sixth transistors are also in the reverse conducting mode. Contrary to this, when the memory cell is selected, the fifth and sixth transistors are in the forward conducting mode.
In the above-mentioned I.sup.2 L memory cell, one of either the third or fourth transistors is conductive, while the other is non-conductive. If the third transistor is conductive, injection currents of the first and second transistors are supplied to the collector (structurally shown as the emitter) and to the base of the third transistor, respectively. In order to change the cell information, the third transistor must be changed to non-conductive. This is done by supplying an emitter current larger than the write threshold current I.sub.wth, and therefore, by bypassing the base current of the third transistor to the base current of the fifth transistor cross-coupled to the third transistor. In this case, the write threshold current I.sub.wth depends on the total injection current I.sub.inj which flows through a common emitter of the first and second transistors. In other words, when the injection current I.sub.inj is large, the write threshold current I.sub.wth is also large.
On the other hand, sink currents, which are explained in more detail below, flow from a selected memory cell directly to non-selected memory cells. The sink currents increase the injection current I.sub.inj of the selected memory cell and, accordingly, increase the write threshold current I.sub.wth, so that the speed of the write operation becomes low.
In order to decrease the sink currents flowing from a selected memory cell into non-selected memory cells, one conventional I.sup.2 L memory device comprises a bit line clamp circuit. The clamp circuit comprises a plurality of pairs of clamp transistors, each pair connected to each of the pairs of bit lines. Usually, a definite voltage is applied to the bases of the clamp transistors so that sink currents of non-selected memory cells are supplied from the clamp transistors, not from the selected memory cell. That is, the potentials of the bit lines are clamped at a level which is hereinafter referred to as a clamp level. Here, it should be noted that the clamp level must be designed to be lower than the potential value for preventing the write current from being decreased and higher than the potential value for preventing the nonselected memory cell from being disturbed. In addition, the deviation of the clamp level is dependent upon the characteristics of the clamp circuit, while the deviations of the two limit values are dependent upon the fluctuation of characteristics of the memory cells induced by manufacturing processes.
However, in the above-mentioned device, since the elements of the clamp circuit are quite different from those of the memory cells, the deviation of the clamp level induced by manufacturing processes and temperature fluctuation is different from those of the two limit values. As a result, if it happens that the clamp level deviates from a range between the two limit values which is relatively small, then the device cannot be reliably operated.